1. Field of the Invention
The invention relates to digital signal processing, and more particularly to a method and system of digital phase calibration for a TV decoder.
2. Description of the Related Art
Digital display units (e.g., flat panel monitors) are often used for displaying images encoded and transmitted in analog signals. An image source (typically including a digital to analog converter) generates an analog signal representing images according to widely used standards such as VGA or SVGA.
An analog display signal typically comprises a display data signal and associated synchronization signals. The display data signal may be viewed as a series of successive portions in the time domain, each portion generated from a pixel data element representing a point of an image. The image portions are typically generated under the control of a source clock, which drives a digital to analog converter (DAC). The DAC generates the analog display data according to the source clock signal.
FIG. 1 is a block diagram of a conventional display unit, disclosed in U.S. Pat. No. 6,483,447.
The digital display unit may comprise analog to digital converter (ADC) 110, phase adjuster 120, time error detector 130, clock generator 140, variable delay 150, panel interface 160, and digital display screen 170. Digital display screen 170 comprises discrete points commonly referred to as pixels. Each pixel can generally be controlled individually, and all the pixels may be activated to various degrees to display an image on a display screen 170. Panel interface 160 receives digital pixel data elements representing an image from ADC 110, and generates electrical signals compatible with the display screen 170 for displaying images represented by the pixel data elements.
Clock generator 140 may generate a synchronized clock signal based on the synchronization signals. It is often desirable that the synchronized clock signal has the same phase and frequency as a source clock used to generate the accompanying display data signal. The frequency and phase of synchronized clock signal 145 may be determined by the synchronization signals. A phase adjustment circuit may be used to adjust the phase of the sampling clock to precisely track the source clock as described in the following. Time error detector 130, phase adjustor 120, and variable delay 150 recurrent an exemplary implementation of the phase adjustment circuit.
Time error detector 130 may examine the display signals to determine the timing of the synchronized clock signal 145 relative to the source clock signal. Time error detector 130 may be implemented in a combination of hardware, software, and/or firmware, but generally requires a structure sufficient for examining the signal level of the analog display data to determine the t timing of the source clock. Time error detector 130 generates a phase error signal indicating whether the phase of the source clock is earlier than, later than or synchronized with clock signal 145 received from clock generator 140. The phase error signal generated from time error detector 130 can be in one of several forms. For example, an integer may be used for identifying the amount of phase lead/lag. A signal line may alternatively be asserted for period of time in proportion to the amount of lead or lag. In another aspect, a pulse may be generated merely to indicate whether the signals have lagged, are leading, or are synchronized.
Phase adjustor 120 receives the phase error signal from time error detector 130 and determines the amount of phase correction during a current clock cycle (of sampling clock 155). Phase adjustor 120 may operate to include characteristic of a filter to ensure that the phase adjustment does not unduly oscillate from lead to lag and vice versa. Phase adjustor 120 may be implemented in one of several ways. For example, phase error 120 may generate a number or analog signals representing the phase correction. A more detailed description of an embodiment of a phase adjustor is provided in the following.
Variable delay 150 adjusts the phase of the sampling clock 155 according to the delay indicated by the output of the phase adjuster 120. Variable delay 150 may be implemented in a known way. In one embodiment, delay lines of multiple taps may be used to delay the sampling clock 155.
Although sampling clock 155 and synchronized clock signal 145 are described as distinct clock signals, phase adjustor 120 may be viewed as adjusting the phase of the sampling clock as will be apparent to those skilled in the relevant arts. The phase adjustment may alternatively be performed by interfacing with a clock generator in a closed-loop without departing from the scope and spirit of the invention as will also be apparent to those skilled in the relevant arts.
Analog-to-digital converter (ADC) 110 samples the display signals to generate pixel data elements representing an image. The pixel data elements may be recovered accurately because the phase of the sampling clock may be adjusted several times within a horizontal line.
FIG. 2 is a schematic view of a system implementing automatic sampling phase control, disclosed in U.S. Pat. No. 6,268,848.
This embodiment comprises an ADC 210, a clock generator 220, a phase controller 230, an automatic system phase controller (ASPC) 240, a controller 250, and a display processing panel 260. The ADC 210 receives an analog display signal RGBIN. The ADC 210 generates digital samples RGBS at a rate determined by the sampling clock (SCLK). The SCLK is a time delay version of a recovered clock (RCLK). The RCLK is generated by a clock generator 220. The clock generator 220 is generally phase locked to the reference signal associated with the analog display signal. The phase controller 230 generates the SCLK by delaying the phase of the RCLK In accordance with the controller 250.
The automatic system phase controller (ASPC) 240 receives the digital samples generated by the ADC 210. The ASPC 240 processes the digital samples and generates a numerical value or statistical estimation for each display frame based on the digital samples. The phase controller 230 is programmed so that the phase of the SCLK is adjusted to maximize the numerical values generated by the ASPC 240. The controller 250 receives an output of the ASPC 240. The display processing and panel 260 receives the digital samples (RGBS) and the SCLK. The display processing and panel 260 typically performs more synchronization and processing of the digital samples before generating a display image.
As described, phase calibration is typically implemented in the ADC by adjusting the phase of the sampling clock. Two categories of the phase calibration method include manual and automatic phase calibration methods. Automatic phase calibration methods may generate better performance than manual phase calibration methods. It is because automatic phase calibration methods determine the best phase by conducting statistical calculation on characteristics of the input signal, whereas manual phase calibration methods may fail to locate an appropriate phase when processing different input signal.